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| this is information on a product in full production. september 2013 docid13773 rev 4 1/68 STA333BW 2.1-channel 40-watt high-eff iciency digital audio system sound terminal? datasheet - production data features ? wide-range supply voltage, 4.5 v to 21.5 v ? three power output configurations: ? 2 channels of ternary pwm (2 x 20 w into 8 ? at 18 v) + pwm output ? 2 channels of ternary pwm (2 x 20 w into 8 ? at 18 v) + ternary stereo line-out ? 2.1 channels of binary pwm (left, right, lfe) (2 x 9 w into 4 ? +1 x 20 w into 8 ? at 18 v) ? ffx with 100-db snr and dynamic range ? scalable ffx modulation index ? selectable 32- to 192-khz input sample rates ? i2c control with selectable device address ? digital gain/attenuati on +48db to -80db with 0.5-db/step resolution ? soft volume update with programmable ratio ? individual channel and master gain/attenuation ? dynamic range compression (drc) or anticlipping mode ? audio presets: ? 15 preset crossover filters ? 5 preset anticlipping modes ? preset night-time listening mode ? individual channel soft/hard mute ? independent channel volume and dsp bypass ? i 2 s input data interface ? input and output channel mapping ? automatic invalid input-detect mute ? up to 5 user-programmable biquads/channel ? three coefficients banks for eq presets storing with fast recall via i2c interface ? bass/treble tones and de-emphasis control ? selectable high-pass filter for dc blocking ? advanced am interference frequency switching and noise suppression modes ? sub channel mix into left and right channels ? selectable high- or low-bandwidth noise-shaping topologies ? selectable clock input ratio ? 96-khz internal processing sample rate ? thermal overload and short-circuit protection technology ? video apps: 576 x f s input mode supported ? pin and sw compatible with sta335bw, sta339bw, sta339bws, sta559bw and sta559bws powersso-36 with exposed pad down (epd) table 1. device summary order code package packaging STA333BW powersso-36 epd tube STA333BW13tr powersso-36 epd tape and reel www.st.com
contents STA333BW 2/68 docid13773 rev 4 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4 electrical specifications for the digital section . . . . . . . . . . . . . . . . . . . . . 10 3.5 electrical specifications for the power section . . . . . . . . . . . . . . . . . . . . . .11 3.6 power-on/off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 serial audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.0.1 timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.0.2 delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.0.3 channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 processing data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 i2c bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1.1 data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1.2 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1.3 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1.4 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.2 multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4.1 current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 docid13773 rev 4 3/68 STA333BW contents 68 6.4.2 current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4.3 random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4.4 random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.1 configuration registers (addr 0x00 to 0x05) . . . . . . . . . . . . . . . . . . . . . . . 21 7.1.1 configuration register a (add r 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.1.2 configuration register b (add r 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1.3 configuration register c (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1.4 configuration register d (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1.5 configuration register e (add r 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1.6 configuration register f (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.2 volume control registers (addr 0x06 - 0x0a) . . . . . . . . . . . . . . . . . . . . . . 39 7.2.1 mute / line output configuration register (addr 0x06) . . . . . . . . . . . . . . . 40 7.2.2 master volume register (addr 0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.2.3 channel 1 volume (addr 0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.2.4 channel 2 volume (addr 0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.2.5 channel 3 / line output volume (addr 0x0a) . . . . . . . . . . . . . . . . . . . . . 41 7.3 audio preset registers (addr 0x0b and 0x0c) . . . . . . . . . . . . . . . . . . . . . 42 7.3.1 audio preset register 1 (addr 0x0b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.3.2 audio preset register 2 (addr 0x0c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.4 channel configuration registers (addr 0x0e - 0x10) . . . . . . . . . . . . . . . . . 44 7.5 tone control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.6 dynamic control registers (addr 0x12 - 0x15) . . . . . . . . . . . . . . . . . . . . . 46 7.6.1 limiter 1 attack / release rate (addr 0x12) . . . . . . . . . . . . . . . . . . . . . . . 46 7.6.2 limiter 1 attack / release threshold (addr 0x13) . . . . . . . . . . . . . . . . . . 46 7.6.3 limiter 2 attack / release rate (addr 0x14) . . . . . . . . . . . . . . . . . . . . . . . 47 7.6.4 limiter 2 attack / release threshold (addr 0x15) . . . . . . . . . . . . . . . . . . 47 7.6.5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.7 user-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . . 52 7.7.1 coefficient address re gister (addr 0x16) . . . . . . . . . . . . . . . . . . . . . . . . 52 7.7.2 coefficient b1 data register bits (addr 0x 17 - 0x19) . . . . . . . . . . . . . . . . 52 7.7.3 coefficient b2 data register bits (addr 0x1a - 0x1c) . . . . . . . . . . . . . . . 52 7.7.4 coefficient a1 data register bits (addr 0x1d - 0x1f) . . . . . . . . . . . . . . . 52 7.7.5 coefficient a2 data register bits (addr 0x 20 - 0x22) . . . . . . . . . . . . . . . . 53 7.7.6 coefficient b0 data register bits (addr 0x 23 - 0x25) . . . . . . . . . . . . . . . . 53 contents STA333BW 4/68 docid13773 rev 4 7.7.7 coefficient read / write control register (addr 0x26) . . . . . . . . . . . . . . . . 53 7.7.8 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.8 variable max power correction registers (addr 0x27 - 0x28) . . . . . . . . . . 58 7.9 distortion compensation registers (addr 0x29 - 0x2a) . . . . . . . . . . . . . . . 58 7.10 fault detect recovery constant registers (addr 0x2b - 0x2c) . . . . . . . . . . 58 7.11 device status register (addr 0x2d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.1 applications schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.2 pll filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.3 typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 docid13773 rev 4 5/68 STA333BW list of figures 68 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. pin connection powersso-36 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 5. power-off sequence for pop-free tu rn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 figure 6. timing diagram for sai interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 7. left and right processing, sectio n 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8. left and right processing, sectio n 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9. write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 11. ocfg = 00 (default value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 12. ocfg = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 13. ocfg = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 14. ocfg = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 15. output mapping scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 16. 2.0 channels (ocfg = 00) pwm sl ots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 17. 2.1 channels (ocfg = 01) pwm sl ots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 18. 2.1 channels (ocfg = 10) pwm sl ots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 19. basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 20. output configuration for stereo btl mode (r l = 8 ?? . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 21. applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 22. powersso-36 power derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 23. powersso-36 epd outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 list of tables STA333BW 6/68 docid13773 rev 4 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 8. timing parameters for slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 table 9. register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10. master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 11. input sampling rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12. internal interpolation ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 13. ir bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 14. thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 15. thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 16. fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 17. serial audio input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 18. serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 19. support serial audio input formats for msb-first (saifb = 0) . . . . . . . . . . . . . . . . . . . . . . . 25 table 20. supported serial audio input formats for lsb-firs t (saifb = 1) . . . . . . . . . . . . . . . . . . . . . 26 table 21. delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 22. channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 23. ffx power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 24. ffx compensating pulse size bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 25. compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 26. overcurrent warning bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 27. high-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 28. de-emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 29. dsp bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 30. postscale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 31. biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 32. dynamic range compression / anticlipping bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 33. zero-detect mute enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 34. submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 35. max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 36. max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 37. noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 38. am mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 39. pwm speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 40. distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 41. zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 42. soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 43. output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 44. output configuration engine selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 45. invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 46. binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 47. lrck double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 48. auto eapd on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 docid13773 rev 4 7/68 STA333BW list of tables 68 table 49. ic power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 50. external amplifier powe r down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 51. line output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 52. master volume offset as a function of mvol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 53. channel volume as a function of cxvol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 54. audio preset gain compression / limiters select ion for amgc[3:2] = 00. . . . . . . . . . . . . . . 43 table 55. am interference frequency switching bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 56. audio preset am switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 57. bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 58. bass management crossover frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 59. tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 60. eq bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 61. volume bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 62. binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 63. channel limiter mapping as a function of cxls bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 64. channel output mapping as a function of cxom bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 65. tone control boost / cut as a function of btc and ttc bits . . . . . . . . . . . . . . . . . . . . . . . . 47 table 66. limiter attack rate vs lxa bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 67. limiter release rate vs lxr bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 68. limiter attack threshold vs lxat bits (ac mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 69. limiter release threshold vs lxrt bits (ac mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 70. limiter attack threshold vs lxat bits (drc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 71. limiter release threshold vs lxrt bits (drc mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 72. ram block for biquads, mixing, scaling, bass ma nagement. . . . . . . . . . . . . . . . . . . . . . . . 56 table 73. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 74. powersso-36 epd dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 75. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 description STA333BW 8/68 docid13773 rev 4 1 description the STA333BW is an integrated solution of digital audio processing, digital amplifier controls and power output stages to create a high-power single-chip ffx digital amplifier with high-quality and high-efficiency. three ch annels of ffx processing are provided. the ffx processor implements the te rnary, binary and binary diff erential processing capabilities of the full ffx processor. the STA333BW is part of the sound terminal ? family that provides full digital audio streaming to the speakers and offers cost ef fectiveness, low power dissipation and sound enrichment. the power section consists of four independe nt half-bridges. these can be configured via digital control to operate in different modes. for example, 2.1 channels can be provided by two half-bridges and a single full-bridge, supplying up to 2 x 9 w + 1 x 20 w of output power or two channels can be provided by two full-bridges, supplying up to 2 x 20 w of output power. the ic can also be configured as 2.1 channel s with 2 x 20 w supplied by the device plus a drive for an external ffx power amplifier, such as sta533wf or sta515w. the serial audio data input interface accepts all possible formats, including the popular i 2 s format. the high-quality conversion from pcm audio to ffx pwm switching provides over 100 db of snr and of dynamic range. also provided in the STA333BW are a full assort ment of digital processing features. this includes up to 5 programmable biquads (eq) per channel. available presets enable a time-to-market advantage by substantially re ducing the amount of software development needed for functions such as audio preset volume loudness, preset volume curves and preset eq settings. there are also new advanc ed am radio interference reduction modes. the drc dynamically equalizes the system to provide a linear frequency speaker response regardless of output power level. figure 1. block diagram protection current / thermal logic regulators bias power control ffx pll volume control channel 1a channel 1b channel 2a channel 2b i 2 s interface power digital dsp i 2 c docid13773 rev 4 9/68 STA333BW pin connections 68 2 pin connections 2.1 connection diagram figure 2. pin connection powersso-36 (top view) 2.2 pin description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 vdd_dig gnd_dig scl sda int_line reset sdi lrcki bicki xti gnd_pll filter_pll vdd_pll pwrdn gnd_dig vdd_dig twarn / out4a eapd / out4b gnd_sub sa test_mode vss vcc_reg out2b gnd2 vcc2 out2a out1b vcc1 gnd1 out1a gnd_reg vdd config out3b / ffx3b out3a / ffx3a d05au1638 ep, exposed pad (device ground) table 2. pin description pin type name description 1 gnd gnd_sub substrate ground 2i sa i 2 c select address (pull-down) 3 i test_mode this pin must be connected to ground (pull-down) 4 i/o vss internal reference at v cc - 3.3 v 5 i/o vcc_reg internal v cc reference 6 o out2b output half-bridge channel 2b 7 gnd gnd2 power negative supply 8 power vcc2 power positive supply 9 o out2a output half-bridge channel 2a 10 o out1b output half-bridge channel 1b pin connections STA333BW 10/68 docid13773 rev 4 11 power vcc1 power positive supply 12 gnd gnd1 power negative supply 13 o out1a output half-bridge channel 1a 14 gnd gnd_reg internal ground reference 15 power vdd internal 3. 3 v reference voltage 16 i config parallel mode command 17 o out3b / ffx3b pwm out channel 3b / external bridge driver 18 o out3a / ffx3a pwm out channel 3a / external bridge driver 19 o eapd / out4b power down for ex ternal bridge / pw m out channel 4b 20 i/o twarn / out4a thermal warning from external bridge (pull-up when input) / pwm out channel 4a 21 power vdd_dig digital supply voltage 22 gnd gnd_dig digital ground 23 i pwrdn power down (pull-up) 24 power vdd_pll positive supply for pll 25 i filter_pll connection to pll filter 26 gnd gnd_pll negative supply for pll 27 i xti pll input clock 28 i bicki i 2 s serial clock 29 i lrcki i 2 s left / right clock 30 i sdi i 2 s serial data channels 1 and 2 31 i reset reset (pull-up) 32 o int_line fault interrupt 33 i/o sda i 2 c serial data 34 i scl i 2 c serial clock 35 gnd gnd_dig digital ground 36 power vdd_dig digital supply voltage - - ep exposed pad for pcb heatsink, to be connected to gnd table 2. pin description (continued) pin type name description docid13773 rev 4 11/68 STA333BW electrical specifications 68 3 electrical specifications 3.1 absolute maximum ratings warning: stresses beyond those listed in table 3 above may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditions? are not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. in the real application, power supplies with nominal values rated within the recommended operating conditions, may experience some rising beyond the maximum operating conditions for a short time when no or very low current is sinked (amplifier in mute state). in this case th e reliability of the device is guaranteed, provided that the absolute maximum ratings are not exceeded. 3.2 thermal data table 3. absolute maximum ratings symbol parameter min typ max unit v cc power supply voltage (pins vccx) -0.3 - 24 v v dd digital supply voltage (pins vdd_dig) -0.3 - 4.0 v v dd pll supply voltage (pin vdd_pll) -0.3 - 4.0 v t op operating junction temperature -20 - 150 c t stg storage temperature -40 - 150 c table 4. thermal data parameter min typ max unit r th j-case thermal resistance junction-case (thermal pad) - - 1.5 c/w t th-sdj thermal shut-down junction temperature - 150 - c t th-w thermal warning temperature - 130 - c t th-sdh thermal shut-down hysteresis - 20 - c r th j-amb thermal resistance junction-ambient (1) 1. see chapter 9: package thermal characteristics on page 64 for details. -24-c/w electrical specifications STA333BW 12/68 docid13773 rev 4 3.3 recommended operating conditions 3.4 electrical specificati ons for the digital section the specifications given in this section are valid for t amb = 25 c unless otherwise specified. table 5. recommended operating condition symbol parameter min typ max unit v cc power supply voltage (vccxa, vccxb) 4.5 - 21.5 v v dd_dig digital supply voltage 2.7 3.3 3.6 v v dd_pll pll supply voltage 2.7 3.3 3.6 v t amb ambient temperature -20 - 70 c table 6. electrical specif ications - digital section symbol parameter conditions min typ max unit i il low level input current without pull-up/down device vi = 0 v - - 1 a i ih high level input current without pull-up/down device vi = vdd_dig = 3.6 v --1a v il low level input voltage - - - 0.2 * vdd_dig v v ih high level input voltage - 0.8 * vdd_dig --v v ol low level output voltage iol = 2 ma - 0.4 * vdd_dig v v oh high level output voltage ioh = 2 ma 0.8 * vdd_dig --v r pu equivalent pull-up/down resistance --50-k ? docid13773 rev 4 13/68 STA333BW electrical specifications 68 3.5 electrical specificati ons for the power section the specifications given in this section are valid for the operating conditions: v cc =18v, f=1khz, f sw = 384 khz, t amb = 25 c and r l = 8 ? , unless otherwise specified. table 7. electrical specifications - power section symbol parameter condit ions min typ max unit po output power btl thd = 1% - 16 - w thd = 10% - 20 - output power se thd = 1%, r l = 4 ? -7- w thd = 10%, r l = 4 ? -9- r dson power p-channel or n-channel mosfet l d = 0.75 a - - 250 m ?? gp power p-channel r dson matching l d = 0.75 a - 100 - % gn power n-channel r dson matching l d = 0.75 a - 100 - % idss power p-channel / n-channel leakage v cc = 20 v - - 1 ? a t r rise time resistive load, see figure 3 below - - 10 ns t f fall time - - 10 ns i vcc supply current from v cc in power down pwrdn = 0 - 0.3 - ? a supply current from v cc in operation pwrdn = 1 - 15 - ma i vdd supply current ffx processing internal clock = 49.152 mhz -55-ma i lim overcurrent limit (1) 2.2 3.0 - a i scp short -circuit protection r l = 0 ? 2.7 3.6 - a v uvp undervoltage protection - - - 4.3 v t min output minimum pulse width no load 20 40 60 ns dr dynamic range - - 100 - db snr signal to noise ratio, ternary mode a-weighted - 100 - db signal to noise ratio binary mode - - 90 - db thd+n total harmonic distortion + noise ffx stereo mode, po = 1 w f=1khz -0.2-% x talk crosstalk ffx stereo mode, <5 khz one channel driven at 1 w, other channel measured -80-db ? peak efficiency, ffx mode po = 2 x 20 w into 8 ? -90- % peak efficiency, binary modes po = 2 x 9 w into 4 ? + 1 x 20 w into 8 ? -87- 1. limit the current if overcurrent warning detect adj ustment bypass is enabled (register bit confc.ocrb on page 29 ). when disabled refer to the i scp . electrical specifications STA333BW 14/68 docid13773 rev 4 figure 3. test circuit tr tf outxy vcc (0.9)*vcc ?vcc (0.1)*vcc t +vcc duty cycle = 50% inxy m58 m57 outxy gnd vdc = vcc/2 v67 r 8 ? + - docid13773 rev 4 15/68 STA333BW electrical specifications 68 3.6 power-on/off sequence figure 4. power-on sequence note: the definition of a stable clock is when f max - f min < 1 mhz. section serial audio input interface format on page 26 gives information on setting up the i 2 s interface. figure 5. power-off sequence for pop-free turn-off don?t care don?t care cmd0 cmd1 cmd2 vcc vdd_dig xti reset i 2 c pwdn tr tc don?t care don?t care cmd0 cmd1 cmd2 vcc vdd_dig xti reset i 2 c pwdn tr tc don?t care don?t care don?t care cmd0 cmd1 cmd2 vcc vdd_dig xti reset i 2 c pwdn tr tc don?t care don?t care cmd0 cmd1 cmd2 vcc vdd_dig xti reset i 2 c pwdn tr tc don?t care don?t care cmd0 cmd1 cmd2 vcc vdd_dig xti reset i 2 c pwdn tr tc don?t care note: no specific vcc and vdd_dig turn ? on sequence is required tr = minimum time between xti master clock stable and reset removal: 1 ms tc = minimum time between reset removal and i 2 c program, sequence start: 1ms don?t care vcc vdd_dig xti don?t care soft mute reg. 0x07 data 0xfe soft eapd reg. 0x05 bit 7 = 0 don?t care fe don?t care don?t care don?t care vcc vdd_dig xti don?t care soft mute reg. 0x07 data 0xfe soft eapd reg. 0x05 bit 7 = 0 don?t care fe don?t care don?t care note: no specific vcc and vdd_dig turn ? off sequence is required serial audio interface STA333BW 16/68 docid13773 rev 4 4 serial audio interface the STA333BW audio serial input interface was designed to interface with standard digital audio components and to accept a number of serial data formats. the STA333BW always acts as the slave when receiving audio input from standard digital audio components. serial data for two channels is provided using three inputs: left/right clock lrcki, serial clock bicki, and serial data sdi12. the sai bit and the saifb bit are used to specify the serial data format. the default serial data format is i 2 s, msb-first. 4.0.1 timings in the STA333BW the bicki and lrcki pins are configured as inputs and they must be supplied by the external peripheral. figure 6. timing diag ram for sai interface 4.0.2 delay serial clock enable to tolerate anomalies in some i 2 s master devices, a pll clock cycle delay can be added to the bicki signal befor e the sai interface. 4.0.3 channel input mapping each channel received via i 2 s can be mapped to any internal processing channel via the channel input mapping regi sters. this allows for flexibility in processing. the default settings of these registers map each i 2 s input channel to its corresponding processing channel. table 8. timing parameters for slave mode symbol parameter min typ max unit t bcy bick cycle time 80 - - ns t bch bick pulse width high 40 - - ns t bcl bick pulse width low 40 - - ns t lrsu lrcki setup time to bicki strobing edge 40 - - ns t lrh lrcki hold time to bicki strobing edge 40 - - ns t lrjt lrcki jitter tolerance 40 ns t bcy t lrh t lrsu lrcki bicki sdi12 t bch t bcl 80% 40% docid13773 rev 4 17/68 STA333BW processing data paths 68 5 processing data paths figure 7 and figure 8 below show the data processing paths inside STA333BW. the whole processing chain is composed of two consec utive sections. in the first one, dual-channel processing is implemented and in the second section each channel is fed into the post mixing block either to generate a third channel (typically used in 2.1 output configuration and with crossover filters enabled) or to have the channels processed by the drc block (2.0 output configuration with crossover filters used to define the cut-off frequency of the two bands). the first section, figure 7 , begins with a 2x oversampling fir filter providing 2 * f s audio processing. then a selectable high-pass filter removes the dc level (enabled if hpb = 0). the left and right channel processing paths can include up to 8 filters, depending on the selected configuration (bits bql, bq5, bq6, bq7 and xo[3:0]). by default, four user programmable, independent filters per chan nel are enabled, plus the preconfigured de-emphasis, bass and treble controls (b ql = 0, bq5 = 0, bq6 = 0, bq7 = 0). if the coefficient sets for the two channels are linked (bql = 1) it is possible to use the de-emphasis, bass and treble filters in a user defined configuration (provided the relevant bqx bits are set). in this case both channels use the same processing coefficients and can have up to seven filters each. if bql = 0 the bqx bits are ignored and the fifth, sixth and seventh filters are configured as de-emphasis, bass and treble controls, respectively. figure 7. left and right processing, section 1 moreover, the common 8th filter can be availabl e on both channels provided the predefined crossover frequencies are not used, xo[3:0] = 0, and the drc is not used. in the second section, figure 8 , mixing and crossover filters are available. if drc is not enabled they are fully user-programmable and allow the generation of a third channel (2.1 outputs). alternatively, in mode drc, these blocks are us ed to split th e sub-band and define the cut-off frequencies of the two bands. a prescaler and a final postscaler allow full control over the signal dynamics before and afte r the filtering stages. a mixer function is also available. from i2s input interface prescale biquad #1 biquad #2 biquad #3 biquad #4 if hpb=0 user defined filters if dspb=0 and c1eqbp=0 x2 fir over l sampling frequency=fs sampling frequency=2xfs from i2s input interface prescale hi-pass filter hi-pass filter biquad #1 biquad #2 biquad #3 biquad #4 de-emph. if demp=0 x2 fir over sampling l sampling frequency=fs sampling frequency=2xfs bass treble if c1tcb=0 btc: bass boost/cut ttc: treble boost/cut prescale hi-pass filter biquad #1 biquad #2 biquad #3 biquad #4 if hpb=0 user defined filters if dspb=0 and c2eqbp=0 x2 fir over l prescale hi-pass filter biquad #1 biquad #2 biquad #3 biquad #4 de-emph. if demp=0 x2 fir over sampling r bass treble if c2tcb=0 btc: bass boost/cut ttc: treble boost/cut if bq5=1 and bql=1 biquad #5 if bq6=1 and bql=1 biquad #6 if bq7=1 and bql=1 biquad #7 if bq5=1 and bql=1 biquad #5 if bq6=1 and bql=1 biquad #6 if bq7=1 and bql=1 biquad #7 from i2s input interface prescale biquad #1 biquad #2 biquad #3 biquad #4 if hpb=0 user defined filters if dspb=0 and c1eqbp=0 x2 fir over l sampling frequency=fs sampling frequency=2xfs from i2s input interface prescale hi-pass filter hi-pass filter hi-pass filter hi-pass filter biquad #1 biquad #2 biquad #3 biquad #4 de-emph. if demp=0 x2 fir over sampling l sampling frequency=fs sampling frequency=2xfs bass treble if c1tcb=0 btc: bass boost/cut ttc: treble boost/cut prescale hi-pass filter biquad #1 biquad #2 biquad #3 biquad #4 if hpb=0 user defined filters if dspb=0 and c2eqbp=0 x2 fir over l prescale hi-pass filter biquad #1 biquad #2 biquad #3 biquad #4 de-emph. if demp=0 x2 fir over sampling r bass treble if c2tcb=0 btc: bass boost/cut ttc: treble boost/cut if bq5=1 and bql=1 biquad #5 if bq6=1 and bql=1 biquad #6 if bq7=1 and bql=1 biquad #7 if bq5=1 and bql=1 biquad #5 if bq6=1 and bql=1 biquad #6 if bq7=1 and bql=1 biquad #7 processing data paths STA333BW 18/68 docid13773 rev 4 figure 8. left and right processing, section 2 crossover frequency determined by xo setting user defined if xo=0000 r l + + + c1mx2 c2mx1 c2mx2 c3mx1 c3mx2 c1mx1 hi-pass xo filter hi-pass xo filter lo-pass xo filter user-defined mix coefficients vol and limiter vol and limiter vol and limiter post scale post scale post scale crossover frequency determined by xo setting user defined if xo=0000 r l + + + c1mx2 c2mx1 c2mx2 c3mx1 c3mx2 c1mx1 hi-pass xo filter hi-pass xo filter lo-pass xo filter user-defined mix coefficients vol and limiter vol and limiter vol and limiter post scale post scale post scale docid13773 rev 4 19/68 STA333BW i2c bus specification 68 6 i2c bus specification the STA333BW supports the i 2 c protocol via the input ports scl and sda_in (master to slave) and the output port sda_out (slave to master). this protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. the device that controls the data tran sfer is known as the master and the other as the slave. the master always starts the tr ansfer and provides the serial clock for synchronization. the STA333BW is always a slave device in all of its communications. it supports up to 400 kb/s (fast-mode bit rate). for correct operation of the i 2 c interface ensure that the mast er clock generated by the pll has a frequency at least 10 times higher than the frequency of the applied scl clock. 6.1 communication protocol 6.1.1 data transition or change data changes on the sda line must only occur when the clock scl is low. a sda transition while the clock is high is used to identify a start or stop condition. 6.1.2 start condition start is identified by a high to low transition of the data bus, sda, while the clock, scl, is stable in the high state. a start conditi on must precede any command for data transfer. 6.1.3 stop condition stop is identified by low to hi gh transition of sda while scl is stable in the high state. a stop condition terminates communication between STA333BW and the bus master. 6.1.4 data input during the data input the STA333BW samples th e sda signal on the rising edge of scl. for correct device operation the sda signal must be stable during the rising edge of the clock and the data can change only when the scl line is low. 6.2 device addressing to start communication between the master an d the STA333BW, the master must initiate with a start condition. following this, the mast er sends onto the sda line 8-bits (msb first) corresponding to the device select address and read or write mode bit. the seven most significant bits are the device address identifiers, corresponding to the i 2 c bus definition. in the STA333BW the i 2 c interface has two device addresses depending on the sa pin configuration, 0x38 when sa = 0, and 0x3a when sa = 1. the eighth bit (lsb) identifies a read or write operation (r/w); this is set to 1 for read and to 0 for write. after a start condition the sta3 33bw identifies the device address on the sda bus and if a match is found, acknowledge s the identification during the 9th bit time frame. the byte following the device identifica tion is the address of a device register. i2c bus specification STA333BW 20/68 docid13773 rev 4 6.3 write operation following the start condition the master sends a device select code with the rw bit set to 0. the STA333BW acknowledges this and then waits for the byte of internal address. after receiving the internal byte address the STA333BW again responds with an acknowledgment. 6.3.1 byte write in the byte write mode the master sends on e data byte, this is acknowledged by the STA333BW. the master then terminates the transfer by generating a stop condition. 6.3.2 multi-byte write the multi-byte write modes can start from any internal address. the master generating a stop condition terminates the transfer. figure 9. write mode sequence 6.4 read operation 6.4.1 current address byte read following the start condition the master sends a device select code with the rw bit set to 1. the STA333BW acknowledges this and th en responds by sending one byte of data. the master then terminates the transfer by generating a stop condition. 6.4.2 current address multi-byte read the multi-byte read modes can start from any internal address. sequential data bytes are read from sequential addresses within the STA333BW. the master acknowledges each data byte read and then generates a st op condition terminating the transfer. 6.4.3 random address byte read following the start condition the master sends a device select code with the rw bit set to 0. the STA333BW acknowledges this and th en the master writes the internal address byte. after receiving, the internal byte address the STA333BW again responds with an acknowledgement. the master then initiates another start condition and sends the device select code with the rw bit set to 1. the st a333bw acknowledges this and then responds by sending one byte of data. the master then terminates the transfer by generating a stop condition. dev-addr ack start rw sub-addr ack data in ack stop byte write dev-addr ack start rw sub-addr ack data in ack stop multibyte write data in ack docid13773 rev 4 21/68 STA333BW i2c bus specification 68 6.4.4 random address multi-byte read the multi-byte read modes could start from any internal address. sequential data bytes are read from sequential addresses within the STA333BW. the master acknowledges each data byte read and then generates a st op condition terminating the transfer. figure 10. read mode sequence dev-addr ack start rw data no ack stop current address read dev-addr ack start rw sub-addr ack dev-addr ack stop random address read data no ack start rw dev-addr ack start data ack data ack stop sequential current read data no ack dev-addr ack start rw sub-addr ack dev-addr ack sequential random read data ack start rw data ack no ack stop data rw= high register description STA333BW 22/68 docid13773 rev 4 7 register description note: addresses exceeding the maximum address number must not be written. table 9. register summary addr name d7 d6 d5 d4 d3 d2 d1 d0 0x00 confa fdrb twab twrb ir1 ir0 mcs2 mcs1 mcs0 0x01 confb c2im c1im dscke saifb sai3 sai2 sai1 sai0 0x02 confc ocrb reserved csz3 csz2 csz1 csz0 om1 om0 0x03 confd sme zde drc bql psl dspb demp hpb 0x04 confe sve zce dccv pwms ame nsbw mpc mpcv 0x05 conff eapd pwdn ecle ldte bcle ide ocfg1 ocfg0 0x06 muteloc loc1 loc0 reserved reserved c3m c2m c1m reserved 0x07 mvol mvol[7:0] 0x08 c1vol c1vol[7:0] 0x09 c2vol c2vol[7:0] 0x0a c3vol c3vol[7:0] 0x0b auto1 reserved reserved amgc[1:0] reser ved reserved reserved reserved 0x0c auto2 xo3 xo2 xo1 xo0 amam2 amam1 amam0 amame 0x0d auto3 reserved 0x0e c1cfg c1om1 c1om0 c1ls1 c1ls0 c1bo c1vbp c1eqbp c1tcb 0x0f c2cfg c2om1 c2om0 c2ls1 c2ls0 c2bo c2vbp c2eqbp c2tcb 0x10 c3cfg c3om1 c3om0 c3ls1 c3ls0 c3bo c3vbp reserved reserved 0x11 tone ttc3 ttc2 ttc1 ttc0 btc3 btc2 btc1 btc0 0x12 l1ar l1a3 l1a2 l1a1 l1a0 l1r3 l1r2 l1r1 l1r0 0x13 l1atrt l1at3 l1at2 l1at1 l1at0 l1rt3 l1rt2 l1rt1 l1rt0 0x14 l2ar l2a3 l2a2 l2a1 l2a0 l2r3 l2r2 l2r1 l2r0 0x15 l2atrt l2at3 l2at2 l2at1 l2at0 l2rt3 l2rt2 l2rt1 l2rt0 0x16 cfaddr reserved reserved cfa[5:0] 0x17 b1cf1 c1b[23:16] 0x18 b1cf2 c1b[15:8] 0x19 b1cf3 c1b[7:0] 0x1a b2cf1 c2b[23:16] 0x1b b2cf2 c2b[15:8] 0x1c b2cf3 c2b[7:0] 0x1d a1cf1 c3b[23:16] 0x1e a1cf2 c3b[15:8] docid13773 rev 4 23/68 STA333BW register description 68 7.1 configuration regist ers (addr 0x00 to 0x05) 7.1.1 configuration register a (addr 0x00) master clock select the STA333BW supports sample rates of 32 khz, 44.1 khz, 48 khz, 88.2 khz, 96 khz, 176.4 khz, and 192 khz. therefore the internal clock is: ? 32.768 mhz for 32 khz ? 45.1584 mhz for 44.1 khz, 88.2 khz, and 176.4 khz ? 49.152 mhz for 48 khz, 96 khz, and 192 khz the external clock frequency provided to the xti pin must be a multiple of the input sample frequency (f s ). 0x1f a1cf3 c3b[7:0] 0x20 a2cf1 c4b[23:16] 0x21 a2cf2 c4b[15:8] 0x22 a2cf3 c4b[7:0] 0x23 b0cf1 c5b[23:16] 0x24 b0cf2 c5b[15:8] 0x25 b0cf3 c5b[7:0] 0x26 cfud reserved ra r1 wa w1 0x27 mpcc1 mpcc[15:8] 0x28 mpcc2 mpcc[7:0] 0x29 dcc1 dcc[15:8] 0x2a dcc2 dcc[7:0] 0x2b fdrc1 fdrc[15:8] 0x2c fdrc2 fdrc[7:0] 0x2d status pllul fault uvfault reserved ocfault ocwarn tfault twarn table 9. register summary (continued) addr name d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 fdrb twab twrb ir1 ir0 mcs2 mcs1 mcs0 01100011 table 10. master clock select bit r/w rst name description 0r/w1 mcs0 selects the ratio between the input i 2 s sample frequency and the input clock. 1r/w1 mcs1 2r/w0 mcs2 register description STA333BW 24/68 docid13773 rev 4 the relationship between the input clock and the input sample rate is determined by both the mcsx and the ir (input rate) register bi ts. the mcsx bits determine the pll factor generating the internal clock and the ir bit determines the oversampling ratio used internally. interpolation ratio select the STA333BW has variable interpolation (oversampling) settings such that internal processing and ffx output rates remain consistent. the first processing block interpolates by either 2-times or 1-time (pass-through) or provides a 2-times downsample. the oversampling ratio of this interpolation is determined by the ir bits. table 11. input sampling rates input sample rate fs (khz) ir mcs[2:0] 101 100 011 010 001 000 32, 44.1, 48 00 576 * fs 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs 88.2, 96 01 na 64 * fs 128 * fs 192 * fs 256 * fs 384 * fs 176.4, 192 1x na 32 * fs 64 * fs 96 * fs 128 * fs 192 * fs table 12. internal interpolation ratio bit r/w rst name description 4:3 r/w 00 ir [1:0] selects internal interpolation ratio based on input i 2 s sample frequency table 13. ir bit settings as a function of input sample rate input sample rate fs (khz) ir 1st stage interpolation ratio 32 00 2-times oversampling 44.1 00 2-times oversampling 48 00 2-times oversampling 88.2 01 pass-through 96 01 pass-through 176.4 10 2-times downsampling 192 10 2-times downsampling docid13773 rev 4 25/68 STA333BW register description 68 thermal warning recovery bypass this bit sets the behavior of the ic after a th ermal warning disappears. if twrb is enabled the device automatically restores the normal gain and output limiting is no longer active. if it is disabled the device keeps the ou tput limit active until a reset is asserted or until twrb set to 0. this bit works in conjunction with twab thermal warning adjustment bypass bit twab enables automatic output limiting wh en a power stage thermal warning condition persists for longer than 400ms. when the feat ure is active (twab = 0) the desired output limiting, set through bit twocl (-3 db by defa ult) at address 0x37 in the ram coefficients bank, is applied. the way the limiting acts after the warning condition disappears is controlled by bit twrb. fault detect recovery bypass the on-chip power block provides feedback to the digital controller which is used to indicate a fault condition (either overcurrent or therma l). when fault is asserted, the power control block attempts a recovery from the fault by as serting the 3-state output, holding it for period of time in the range of 0.1 ms to 1 second, as defined by the fault-detect recovery constant register (fdrc registers 0x2b-0x2c), then to ggling it back to normal condition. this sequence is repeated as log as the fault indica tion exists. this feature is enabled by default but can be bypassed by setting the fdrb control bit to 1. the fault condition is also asserted by a low-state pulse of the normally high int_line output pin. 7.1.2 configuration register b (addr 0x01) table 14. thermal warning recovery bypass bit r/w rst name description 5r/w1 twrb 0: thermal warning recovery enabled 1: thermal warning recovery disabled table 15. thermal warning adjustment bypass bit r/w rst name description 6r/w1 twab 0: thermal warning adjustment enabled 1: thermal warning adjustment disabled table 16. fault detect recovery bypass bit r/w rst name description 7 r/w 0 fdrb 0: fault detect recovery enabled 1: fault detect recovery disabled d7 d6 d5 d4 d3 d2 d1 d0 c2im c1im dscke saifb sai3 sai2 sai1 sai0 10000000 register description STA333BW 26/68 docid13773 rev 4 serial audio input interface format serial data interface the STA333BW audio serial input interfaces with standard digital audio components and accepts a number of serial data formats. STA333BW always acts as slave when receiving audio input from standard digital audio componen ts. serial data for two channels is provided using three inputs: left/right clock lrcki, serial clock bicki, and serial data sdi. bits sai and bit saifb are used to specify the serial data format. the default serial data format is i 2 s, msb first. available formats are shown in the tables and figure that follow. serial data first bit table 17. serial audio input interface bit r/w rst name description 0r/w0 sai0 determines the interface format of the input serial digital audio interface. 1r/w0 sai1 2r/w0 sai2 3r/w0 sai3 table 18. serial data first bit saifb format 0 msb-first 1 lsb-first table 19. support serial audio input formats for msb-first (saifb = 0) bicki sai [3:0] saifb interface format 32 * fs 0000 0 i 2 s 15-bit data 0001 0 left / right-justified 16-bit data 48 * fs 0000 0 i 2 s 16 to 23-bit data 0001 0 left-justified 16 to 24-bit data 0010 0 right-justified 24-bit data 0110 0 right-justified 20-bit data 1010 0 right-justified 18-bit data 1110 0 right-justified 16-bit data 64 * fs 0000 0 i 2 s 16 to 24-bit data 0001 0 left-justified 16 to 24-bit data 0010 0 right-justified 24-bit data 0110 0 right-justified 20-bit data 1010 0 right-justified 18-bit data 1110 0 right-justified 16-bit data docid13773 rev 4 27/68 STA333BW register description 68 to make the STA333BW work properly, the serial audio interface lrcki clock must be synchronous to the pll output clock. it means that: ? n-4< = (frequency of pll clock) / (f requency of lrcki) = < n+4 cycles, where n depends on the settings in table 13 on page 24 ? the pll must be locked. if these two conditions are not met, and ide bi t (register 0x05, bit 2) is set to 1, the STA333BW immediately mutes the i 2 s pcm data out (provided to the processing block) and it freezes any active processing task. table 20. supported serial audio input formats for lsb-first (saifb = 1) bicki sai [3:0] saifb interface format 32 * fs 1100 1 i 2 s 15-bit data 1110 1 left/right-justified 16-bit data 48 * fs 0100 1 i 2 s 23-bit data 0100 1 i 2 s 20-bit data 1000 1 i 2 s 18-bit data 1100 1 lsb first i 2 s 16-bit data 0001 1 left-justified 24-bit data 0101 1 left-justified 20-bit data 1001 1 left-justified 18-bit data 1101 1 left-justified 16-bit data 0010 1 right-justified 24-bit data 0110 1 right-justified 20-bit data 1010 1 right-justified 18-bit data 1110 1 right-justified 16-bit data 64 * fs 0000 1 i 2 s 24-bit data 0100 1 i 2 s 20-bit data 1000 1 i 2 s 18-bit data 1100 1 lsb first i 2 s 16-bit data 0001 1 left-justified 24-bit data 0101 1 left-justified 20-bit data 1001 1 left-justified 18-bit data 1101 1 left-justified 16-bit data 0010 1 right-justified 24-bit data 0110 1 right-justified 20-bit data 1010 1 right-justified 18-bit data 1110 1 right-justified 16-bit data register description STA333BW 28/68 docid13773 rev 4 clock desynchronization can happen during STA333BW operation because of source switching or tv channel change. to avoid audio side effects, like click or pop noise, it is strongly recommended to complete the following actions: 1. soft volume change 2. i 2 c read / write instructions while the serial audio interface and the internal pll ar e still synchronous. delay serial clock enable channel input mapping each channel received via i 2 s can be mapped to any internal processing channel via the channel input mapping re gisters. this allows for flexib ility in processi ng. the default settings of these registers maps each i 2 s input channel to its corresponding processing channel. 7.1.3 configuration register c (addr 0x02) ffx power output mode the ffx power output mode selects how the ffx output timing is configured. different power devices use different output modes. table 21. delay serial clock enable bit r/w rst name description 5 r/w 0 dscke 0: no serial clock delay 1: serial clock delay by 1 co re clock cycle to tolerate anomalies in some i 2 s master devices table 22. channel input mapping bit r/w rst name description 6r/w0 c1im 0: processing channel 1 receives left i 2 s input 1: processing channel 1 receives right i 2 s input 7r/w1 c2im 0: processing channel 2 receives left i 2 s input 1: processing channel 2 receives right i 2 s input d7 d6 d5 d4 d3 d2 d1 d0 ocrb reserved csz3 csz2 csz1 csz0 om1 om0 10010111 table 23. ffx power output mode bit r/w rst name description 0 r/w 1 om0 selects configuration of ffx output: 00: drop compensation 01: discrete output stage: tapered compensation 10: full-power mode 11: variable drop compensation (cszx bits) 1r/w1 om1 docid13773 rev 4 29/68 STA333BW register description 68 ffx compensating pulse size register overcurrent warning adjustment bypass the ocrb is used to indicate how STA333BW behaves when an overcurrent warning condition occurs. if ocrb = 0 and the overcu rrent condition happens, the power control block forces an adjustment to the modulation limit (default is -3 db) in an attempt to eliminate the overcurrent warning condition. once the overcurrent warning clipping adjustment is applied, it remains in this state until reset is applied or ocrb is set to 1. the level of adjustment can be changed via the twocl (thermal warning / overcurrent limit) setting at address 0x37 of the user defined coefficient ram ( section 7.7.7 on page 55 ). the ocrb can be enabled when the output bridge is already on. 7.1.4 configuration register d (addr 0x03) high-pass filter bypass table 24. ffx compensating pulse size bits bit r/w rst name description 2r/w1 csz0 when om[1,0] = 11, this register determines the size of the ffx compensating pulse from 0 clock ticks to 15 clock periods. 3r/w1 csz1 4r/w1 csz2 5r/w0 csz3 table 25. compensating pulse size csz[3:0] compensating pulse size 0000 0 ns (0 tick) compensating pulse size 0001 20 ns (1 tick) clock period compensating pulse size ?? 1111 300 ns (15 tick) clock period compensating pulse size table 26. overcurrent warning bypass bit r/w rst name description 7 r/w 1 ocrb 0: overcurrent warning adjustment enabled 1: overcurrent warning adjustment disabled d7 d6 d5 d4 d3 d2 d1 d0 sme zde drc bql psl dspb demp hpb 01000000 table 27. high-pass filter bypass bit r/w rst name description 0 r/w 0 hpb 1: bypass internal ac coupling digital high-pass filter register description STA333BW 30/68 docid13773 rev 4 the STA333BW features an internal digital high-p ass filter for the purpose of ac coupling. the purpose of this filter is to prevent dc si gnals from passing through a ffx amplifier. dc signals can cause speaker damage. when hpb = 0, this filter is enabled. de-emphasis dsp bypass setting the dspb bit bypasses th e eq function of the STA333BW. postscale link postscale function can be used for power-supply error correction. for multi-channel applications running off the same power-suppl y, the postscale values can be linked to the value of channel 1 for ease of use and update the values faster. biquad coefficient link for ease of use, all channels can use the biquad coefficients loaded into the channel-1 coefficient ram space by setting the bql bit to 1. therefore, any eq updates only have to be performed once. table 28. de-emphasis bit r/w rst name description 1r/w0 demp 0: no de-emphasis 1: enable de-emphasis on all channels table 29. dsp bypass bit r/w rst name description 2 r/w 0 dspb 0: normal operation 1: bypass of biquad and bass / treble functions table 30. postscale link bit r/w rst name description 3r/w0 psl 0: each channel uses individual postscale value 1: each channel uses channel 1 postscale value table 31. biquad coefficient link bit r/w rst name description 4r/w0 bql 0: each channel uses coefficient values 1: each channel uses channel 1 coefficient values docid13773 rev 4 31/68 STA333BW register description 68 dynamic range compression / anticlipping bit both limiters can be used in one of two ways, anticlipping or dynamic range compression. when used in anticlipping mode the limiter thre shold values are constant and dependent on the limiter settings. in dynami c range compression mode the limiter threshold values vary with the volume settings allowing a nighttime list ening mode that provides a reduction in the dynamic range regardless of the volume level. zero-detect mute enable setting the zde bit enables the zero-detect auto matic mute. the zero-detect circuit looks at the data for each processing channel at th e output of the crossover (bass management) filter. if any channel receives 2048 consecutiv e zero value samples (regardless of fs) then that individual channel is muted if this function is enabled. submix mode enable 7.1.5 configuration register e (addr 0x04) max power correction variable table 32. dynamic range compression / anticlipping bit bit r/w rst name description 5 r/w 0 drc 0: limiters act in anticlipping mode 1: limiters act in dynamic range compression mode table 33. zero-detect mute enable bit r/w rst name description 6r/w1 zde 0: automatic zero- detect mute disabled 1: automatic zero- detect mute enabled table 34. submix mode enable bit r/w rst name description 7r/w0 sme 0: submix into left / right disabled 1: submix into left / right enabled d7 d6 d5 d4 d3 d2 d1 d0 sve zce dccv pwms ame nsbw mpc mpcv 11000010 table 35. max power correction variable bit r/w rst name description 0r/w0 mpcv 0: use standard mpc coefficient 1: use mpcc bits for mpc coefficient register description STA333BW 32/68 docid13773 rev 4 max power correction setting the mpc bit turns on special processing that corrects the STA333BW power device at high power. this mode sh ould lower the thd+n of a full ffx system at maximum power output and slightly below. if enabled, mpc is operational in all output modes except tapered (om[1,0] = 01) and binary. when ocfg = 00, mpc has no effect on channels 3 and 4, the line-out channels. noise-shaper bandwidth selection am mode enable STA333BW features a ffx proc essing mode that minimizes the amount of noise generated in frequency range of am radio. this mode is intended for use when ffx is operating in a device with an am tuner active. the snr of the ffx processing is reduced to approximately 83 db in this mode, which is still greater than the snr of am radio. pwm speed mode table 36. max power correction bit r/w rst name description 1r/w1 mpc 0: function disabled 1: enables power bridge correction for thd reduction near maximum power output. table 37. noise-shaper bandwidth selection bit r/w rst name description 2 r/w 0 nsbw 1: third-order ns 0: fourth-order ns table 38. am mode enable bit r/w rst name description 3r/w0 ame 0: normal ffx operation. 1: am reduction mode ffx operation table 39. pwm speed mode bit r/w rst name description 4r/w0 pwms 0: normal speed (384 khz) all channels 1: odd speed (341.3 khz) all channels docid13773 rev 4 33/68 STA333BW register description 68 distortion compensation variable enable zero-crossing volume enable the zce bit enables zero-crossing volume adjustments. when volume is adjusted on digital zero-crossings no clicks are audible. soft volume update enable 7.1.6 configuration re gister f (addr 0x05) output configuration table 40. distortion compensation variable enable bit r/w rst name description 5 r/w 0 dccv 0: use preset dc coefficient 1: use dcc coefficient table 41. zero-crossing volume enable bit r/w rst name description 6r/w1 zce 1: volume adjustments only occur at digital zero- crossings 0: volume adjustments occur immediately table 42. soft volume update enable bit r/w rst name description 7 r/w 1 sve 1: volume adjustments ramp according to svup / svdw settings 0: volume adjustments occur immediately d7 d6 d5 d4 d3 d2 d1 d0 eapd pwdn ecle ldte bcle ide ocfg1 ocfg0 01011100 table 43. output configuration bit r/w rst name description 0 r/w 0 ocfg0 selects the output configuration 1 r/w 0 ocfg1 register description STA333BW 34/68 docid13773 rev 4 note: to the left of the arrow is the processing channel. when using chan nel output mapping, any of the three processing channel outputs can be used for any of the three inputs. figure 11. ocfg = 00 (default value) table 44. output configuration engine selection ocfg[1:0] output configuration config pin 00 2 channel (full-bridge) power, 2 channel data-out: 1a/1b ? 1a/1b 2a/2b ? 2a/2b lineout1 ? 3a/3b lineout2 ? 4a/4b line out configuration de termined by loc register 0 01 2 (half-bridge), 1(full-bridge) on-board power: 1a ? 1a binary 0 2a ? 1b binary 90 3a/3b ? 2a/2b binary 45 1a/b ? 3a/b binary 0 2a/b ? 4a/b binary 90 0 10 2 channel (full-bridge) power, 1 channel ffx: 1a/1b ? 1a/1b 2a/2b ? 2a/2b 3a/3b ? 3a/3b eapdext and twarnext active 0 11 1 channel mono-parallel: 3a ? 1a/1b w/ c3bo 45 3b ? 2a/2b w/ c3bo 45 1a/1b ? 3a/3b 2a/2b ? 4a/4b 1 half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 2 channel 1 lpf lineout1 out3b lpf lineout2 out4b out4a out3a half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 2 channel 1 lpf lineout1 out3b lpf lineout2 out4b out4a out3a docid13773 rev 4 35/68 STA333BW register description 68 figure 12. ocfg = 01 figure 13. ocfg = 10 figure 14. ocfg = 11 the STA333BW can be configured to support different output configurations. for each pwm output channel a pwm slot is defined. a pwm slot is always 1 / (8 * fs) seconds length. the pwm slot define the maximum exte nsion for pwm rise and fall edge, that is, rising edge as far as the falling edge cann ot range outside pwm slot boundaries. half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 3 channel 1 channel 2 half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 3 channel 1 channel 2 half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 2 channel 1 power device out3b out3a eapd channel 3 half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 2 channel 1 power device out3b out3a eapd channel 3 half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 3 out3b out4b out4a out3a channel 1 channel 2 half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 3 out3b out4b out4a out3a channel 1 channel 2 register description STA333BW 36/68 docid13773 rev 4 figure 15. output mapping scheme for each configuration the pwm signals from the digital driver are mapped in different ways to the power stage: ffx ? modulator remap ffx1a ffx1 b ffx2 a ffx 2b out1a out1b out2a out2b power bridge out1a out1b out2a out2b ffx3 a ffx3b ffx4 a ffx 4b out3a out3b out4a out4b ffx ? modulator remap ffx1a ffx1 b ffx2 a ffx 2b out1a out1b out2a out2b power bridge out1a out1b out2a out2b ffx3 a ffx3b ffx4 a ffx 4b out3a out3b out4a out4b ffx ? modulator remap ffx1a ffx1 b ffx2 a ffx 2b out1a out1b out2a out2b power bridge out1a out1b out2a out2b ffx3 a ffx3b ffx4 a ffx 4b out3a out3b out4a out4b ffx ? modulator remap ffx1a ffx1 b ffx2 a ffx 2b out1a out1b out2a out2b power bridge out1a out1b out2a out2b ffx3 a ffx3b ffx4 a ffx ? modulator remap ffx1a ffx1 b ffx2 a ffx 2b out1a out1b out2a out2b power bridge out1a out1b out2a out2b ffx3 a ffx3b ffx4 a ffx 4b out3a out3b out4a out4b ffx ? modulator remap ffx1a ffx1 b ffx2 a ffx 2b out1a out1b out2a out2b power bridge out1a out1b out2a out2b ffx3 a ffx3b ffx4 a ffx 4b out3a out3b out4a out4b docid13773 rev 4 37/68 STA333BW register description 68 2.0 channels, two full-bridges (ocfg = 00) mapping: ? ffx1a -> out1a ? ffx1b -> out1b ? ffx2a -> out2a ? ffx2b -> out2b ? ffx3a -> out3a ? ffx3b -> out3b ? ffx4a -> out4a ? ffx4b -> out4b default modulation: ? ffx1a / 1b configured as ternary ? ffx2a / 2b configured as ternary ? ffx3a / 3b configured as lineout ternary ? ffx4a / 4b configured as lineout ternary on channel 3 line out (loc bits = 00) the same data as channel 1 processing is sent. on channel 4 line out (loc bits = 00) the same data as channel 2 processing is sent. in this configuration, volume control or eq have no effect on channels 3 and 4. in this configuration the pwm slot phase is the following as shown in figure 16 . figure 16. 2.0 channels (ocfg = 00) pwm slots out1a out1b out2a out2b out3a out3b out4a out4b out1a out1b out2a out2b out3a out3b out4a out4b register description STA333BW 38/68 docid13773 rev 4 2.1 channels, two half-bridges + one full-bridge (ocfg = 01) mapping: ? ffx1a -> out1a ? ffx2a -> out1b ? ffx3a -> out2a ? ffx3b -> out2b ? ffx1a -> out3a ? ffx1b -> out3b ? ffx2a -> out4a ? ffx2b -> out4b modulation: ? ffx1a / 1b configured as binary ? ffx2a / 2b configured as binary ? ffx3a / 3b configured as binary ? ffx4a / 4b configured as binary in this configuration, channel 3 has full co ntrol (volume, eq, etc?). on out3 / out4 channels the channel 1 and channel 2 pwm are replicated. in this configuration the pwm slot phase is the following as shown in figure 17 . figure 17. 2.1 channels (ocfg = 01) pwm slots out1a out2a out2b out3a out3b out1b out4a out4b out1a out2a out2b out3a out3b out1b out4a out4b out1a out2a out2b out3a out3b out1b out4a out4b out1a out2a out2b out3a out3b out1b out1a out2a out2b out3a out3b out1b out4a out4b out1a out2a out2b out3a out3b out1b out4a out4b docid13773 rev 4 39/68 STA333BW register description 68 2.1 channels, two full-bridges + one external full-bridge (ocfg = 10) mapping: ? ffx1a -> out1a ? ffx1b -> out1b ? ffx2a -> out2a ? ffx2b -> out2b ? ffx3a -> out3a ? ffx3b -> out3b ? eapd -> out4a ? twarn -> out4b default modulation: ? ffx1a / 1b configured as ternary ? ffx2a / 2b configured as ternary ? ffx3a / 3b configured as ternary ? ffx4a / 4b is not used in this configuration, channel 3 has full cont rol (volume, eq, etc?). on out4 channel the external bridge control signals are muxed. in this configuration the pwm slot phase is the following as shown in figure 18 . figure 18. 2.1 channels (ocfg = 10) pwm slots out1a out1b out2a out2b out3a out3b out1a out1b out2a out2b out3a out3b out1a out1b out2a out2b out3a out3b out1a out1b out2a out2b out3a out3b register description STA333BW 40/68 docid13773 rev 4 invalid input detect mute enable setting the ide bit enables this fu nction, which looks at the input i 2 s data and automatically mutes if the signals are perceived as invalid. binary output mode clock loss detection detects loss of input mclk in binary mode and will output 50% duty cycle. lrck double trigger protection ldte, when enabled, prevents double trigger of lrclk on instable i2s input. auto eapd on clock loss when active, issues a power device power down signal (eapd) on clock loss detection. ic power down table 45. invalid input detect mute enable bit r/w rst name description 2r/w1 ide 0: disables the automatic invalid input detect mute 1: enables the automatic invalid input detect mute table 46. binary output mode clock loss detection bit r/w rst name description 3r/w1 bcle 0: binary output mode clock loss detection disabled 1: binary output mode clock loss detection enable table 47. lrck double trigger protection bit r/w rst name description 4r/w1 ldte 0: lrclk double trigger protection disabled 1: lrclk double trigger protection enabled table 48. auto eapd on clock loss bit r/w rst name description 5r/w0 ecle 0: auto eapd on clock loss not enabled 1: auto eapd on clock loss table 49. ic power down bit r/w rst name description 6r/w1 pwdn 0: ic power down low-power condition 1: ic normal operation docid13773 rev 4 41/68 STA333BW register description 68 the pwdn register is used to place the ic in a low-power state. when pwdn is written as 0, the output begins a soft-mute. after the mute condition is reached, eapd is asserted to power down the power-stage, then the master clock to all internal hardware expect the i 2 c block is gated. this places the ic in a very low power consumption state. external amplifier power down the eapd register di rectly disables / enables th e internal powe r circuitry. when eapd = 0, the internal power section is placed in a low-power state (disabled). this register also controls the ffx4b / eapd output pin when ocfg = 10. 7.2 volume control regis ters (addr 0x06 - 0x0a) the volume structure of the STA333BW consists of individual volume registers for each channel and a master volume register that pr ovides an offset to each channels volume setting. the individual channel volumes ar e adjustable in 0.5 db steps from +48 db to -80 db. as an example if c3vol = 0x00 or +48 db and mvol = 0x18 or -12 db, then the total gain for channel 3 = +36 db. the channel mutes provide a ?soft mute? wit h the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (approximately 96 khz). a ?hard (instantaneous) mute? can be obtained by programming a value of 0xff (255) in any channel volume register. when volume offsets are provided via the master volume register any channel whose total volu me is less than -80 db is muted. all changes in volume take place at zero-crossings when zce = 1 ( configuration register e (addr 0x04) ) on a per channel basis as this creates the smoothest possible volume transitions. when zce = 0, volu me updates occur immediately. table 50. external amplifier power down bit r/w rst name description 7r/w0 eapd 0: external power stage power down active 1: normal operation register description STA333BW 42/68 docid13773 rev 4 7.2.1 mute / line output confi guration register (addr 0x06) line output is only active when ocfg = 00. in this case loc determines the line output configuration. the source of the line output is always the channel 1 and 2 inputs. 7.2.2 master volume register (addr 0x07) 7.2.3 channel 1 volume (addr 0x08) 7.2.4 channel 2 volume (addr 0x09) d7 d6 d5 d4 d3 d2 d1 d0 loc1 loc0 reserved reserved c3m c2m c1m reserved 00000000 table 51. line output configuration loc[1:0] line output configuration 00 line output fixed - no volume, no eq 01 line output variable - channel 3 volume effects line output, no eq 10 line output variable with eq - channel 3 volume effects line output d7 d6 d5 d4 d3 d2 d1 d0 mvol7 mvol6 mvol5 mvol4 mvol3 mvol2 mvol1 mvol0 11111111 table 52. master volume offset as a function of mvol mvol[7:0] volume offset from channel value 00000000 (0x00) 0 db 00000001 (0x01) -0.5 db 00000010 (0x02) -1 db ?? 01001100 (0x4c) -38 db ?? 11111110 (0xfe) -127.5 db 11111111 (0xff) default mute, not to be used during operation d7 d6 d5 d4 d3 d2 d1 d0 c1vol7 c1vol6 c1vol5 c1vol4 c1vol3 c1vol2 c1vol1 c1vol0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c2vol7 c2vol6 c2vol5 c2vol4 c2vol3 c2vol2 c2vol1 c2vol0 01100000 docid13773 rev 4 43/68 STA333BW register description 68 7.2.5 channel 3 / line output volume (addr 0x0a) d7 d6 d5 d4 d3 d2 d1 d0 c3vol7 c3vol6 c3vol5 c3vol4 c3vol3 c3vol2 c3vol1 c3vol0 01100000 table 53. channel volume as a function of cxvol cxvol[7:0] volume 00000000 (0x00) +48 db 00000001 (0x01) +47.5 db 00000010 (0x02) +47 db ?? 01011111 (0x5f) +0.5 db 01100000 (0x60) 0 db 01100001 (0x61) -0.5 db ?? 11010111 (0xd7) -59.5 db 11011000 (0xd8) -60 db 11011001 (0xd9) -61 db 11011010 (0xda) -62 db ?? 11101100 (0xec) -80 db 11101101 (0xed) hard channel mute ?? 11111111 (0xff) hard channel mute register description STA333BW 44/68 docid13773 rev 4 7.3 audio preset register s (addr 0x0b and 0x0c) 7.3.1 audio preset re gister 1 (addr 0x0b) using amgc[1:0] bits, attack and release thres holds and rates are automatically configured to properly fit application specific c onfigurations. they are defined below in table 54 . 7.3.2 audio preset re gister 2 (addr 0x0c) am interference frequency switching d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved amgc[1] amgc[0] re served reserved reserved reserved 10000000 table 54. audio preset gain compression / limiters selection for amgc[3:2] = 00 amgc[1:0] mode 00 user programmable gc 01 ac no clipping 2.1 10 ac limited clipping (10%) 2.1 11 drc night-time listening mode 2.1 d7 d6 d5 d4 d3 d2 d1 d0 xo3 xo2 xo1 xo0 amam2 amam1 amam0 amame 00000000 table 55. am interference frequency switching bits bit r/w rst name description 0 r/w 0 amame audio preset am enable 0: switching frequency determined by pwms setting 1: switching frequency determined by amam settings table 56. audio preset am switching frequency selection amam[2:0] 48 khz / 96 khz input fs 44.1 khz / 88.2 khz input fs 000 0.535 mhz - 0.720 mhz 0.535 mhz - 0.670 mhz 001 0.721 mhz - 0.900 mhz 0.671 mhz - 0.800 mhz 010 0.901 mhz - 1.100 mhz 0.801 mhz - 1.000 mhz 011 1.101 mhz - 1.300 mhz 1.001 mhz - 1.180 mhz 100 1.301 mhz - 1.480 mhz 1.181 mhz - 1.340 mhz 101 1.481 mhz - 1.600 mhz 1.341 mhz - 1.500 mhz 110 1.601 mhz - 1.700 mhz 1.501 mhz - 1.700 mhz docid13773 rev 4 45/68 STA333BW register description 68 bass management crossover table 57. bass management crossover bit r/w rst name description 4r/w0 xo0 selects the bass-management crossover frequency. a 1st-order hign-pass filter (channels 1 and 2) or a 2nd-order low-pass filter (channel 3) at the selected frequency is performed. 5r/w0 xo1 6r/w0 xo2 7r/w0 xo3 table 58. bass management crossover frequency xo[3:0] crossover frequency 0000 user-defined ( section 7.7.8 on page 56 ) 0001 80 hz 0010 100 hz 0011 120 hz 0100 140 hz 0101 160 hz 0110 180 hz 0111 200 hz 1000 220 hz 1001 240 hz 1010 260 hz 1011 280 hz 1100 300 hz 1101 320 hz 1110 340 hz 1111 360 hz register description STA333BW 46/68 docid13773 rev 4 7.4 channel configuration registers (addr 0x0e - 0x10) tone control bypass tone control (bass / treble) can be bypassed on a per channel basis for channels 1 and 2. eq bypass eq control can be bypassed on a per channel basis for channels 1 and 2. if eq control is bypassed on a given channel the prescale and all filters (high-pass, biquads, de-emphasis, bass, treble in any combination) are bypassed for that channel. volume bypass each channel contains an individual channel volume bypass. if a particular channel has volume bypassed via the cxvbp = 1 register then only the chann el volume sett ing for that particular channel affects the volume setting, the master volume setting has no effect on that channel. d7 d6 d5 d4 d3 d2 d1 d0 c1om1 c1om0 c1ls1 c1ls0 c1bo c1vpb c1eqbp c1tcb 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2om1 c2om0 c2ls1 c2ls0 c2bo c2vpb c2eqbp c2tcb 01000000 d7 d6 d5 d4 d3 d2 d1 d0 c3om1 c3om0 c3ls1 c3ls0 c3bo c3vpb reserved reserved 10000000 table 59. tone control bypass cxtcb mode 0 perform tone control on channel x - normal operation 1 bypass tone control on channel x table 60. eq bypass cxeqbp mode 0 perform eq on channel x - normal operation 1 bypass eq on channel x table 61. volume bypass register cxvbp mode 0 normal volume operations 1 volume is by-passed docid13773 rev 4 47/68 STA333BW register description 68 binary output enable registers each individual channel output can be set to output a binary pwm stream. in this mode output a of a channel is considered the positi ve output and output b is negative inverse. limiter select limiter selection can be made on a per-channel basis according to the channel limiter select bits. . output mapping output mapping can be performed on a per ch annel basis according to the cxom channel output mapping bits. each input into the out put configuration engine can receive data from any of the three processing channel outputs. . table 62. binary output enable registers cxbo mode 0 ffx output operation 1 binary output table 63. channel limiter mappi ng as a function of cxls bits cxls[1:0] channel limiter mapping 00 channel has limiting disabled 01 channel is mapped to limiter #1 10 channel is mapped to limiter #2 table 64. channel output mapping as a function of cxom bits cxom[1:0] channel x output source from 00 channel1 01 channel 2 10 channel 3 register description STA333BW 48/68 docid13773 rev 4 7.5 tone control re gister (addr 0x11) tone control 7.6 dynamic control regis ters (addr 0x12 - 0x15) 7.6.1 limiter 1 attack / release rate (addr 0x12) 7.6.2 limiter 1 attack / release threshold (addr 0x13) d7 d6 d5 d4 d3 d2 d1 d0 ttc3 ttc2 ttc1 ttc0 btc3 btc2 btc1 btc0 01110111 table 65. tone control boost / cut as a function of btc and ttc bits btc[3:0], ttc[3:0] boost / cut 0000 -12 db 0001 -12 db 0010 -10 db ?? 0101 -4 db 0110 -2 db 0111 0 db 1000 +2 db 1001 +4 db ?? 1100 +10 db 1101 +12 db 1110 +12 db 1111 +12 db d7 d6 d5 d4 d3 d2 d1 d0 l1a3 l1a2 l1a1 l1a0 l1r3 l1r2 l1r1 l1r0 01101010 d7 d6 d5 d4 d3 d2 d1 d0 l1at3 l1at2 l1at1 l1at0 l1rt3 l1rt2 l1rt1 l1rt0 01101001 docid13773 rev 4 49/68 STA333BW register description 68 7.6.3 limiter 2 attack / release rate (addr 0x14) 7.6.4 limiter 2 attack / release threshold (addr 0x15) 7.6.5 description the STA333BW includes two independent limiter blocks. the purpose of the limiters is to automatically reduce the dynamic range of a re cording to prevent the outputs from clipping in anticlipping mode or to actively reduce the dynamic range for a better listening environment such as a night-time listening mode which is often needed for dvds. the two modes are selected via the drc bit in configuration register e (addr 0x04) on page 31 . each channel can be mapped to either limiter or no t mapped, meaning th at channel will clip when 0 dbfs is exceeded. each limiter looks at the present value of each channel that is mapped to it, selects the maximum absolute va lue of all these channels, performs the limiting algorithm on that value, and then if needed adjusts the gain of the mapped channels in unison. figure 19. basic limiter and volume flow diagram the limiter attack thresholds are determined by the lxat registers. it is recommended in anticlipping mode to set this to 0 dbfs, which corresponds to the maximum unclipped output power of a ffx am plifier. since gain can be added digitally within the STA333BW it is possible to exceed 0 dbfs or any other lxat setting, when this occurs, the limiter, when active, automatically starts reducing the gain. the rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that lim iter. gain reduction occurs on a peak-detect algorithm. the limiter release thresholds are determined by the lxrt registers. the release of limiter, when the gain is again increased, is dependent on a rms-detect algorithm. the output of the volume / limiter bl ock is passed through a rms filter. the output of this filter is compared to the release th reshold, determined by the release threshold register. when the rms filter output falls belo w the release threshold, the gain is again increased at a rate dependent upon the release rate register. the gain can never be increased past its set value and, therefore, the release only occurs if the limiter has already d7 d6 d5 d4 d3 d2 d1 d0 l2a3 l2a2 l2a1 l2a0 l2r3 l2r2 l2r1 l2r0 01101010 d7 d6 d5 d4 d3 d2 d1 d0 l2at3 l2at2 l2at1 l2at0 l2rt3 l2rt2 l2rt1 l2rt0 01101001 attenuation saturation rms limiter gain gain / volume input output + attenuation saturation rms limiter gain gain / volume input output + register description STA333BW 50/68 docid13773 rev 4 reduced the gain. the release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as over limiting can reduce the dynamic range to virtually zero and cause program material to sound ?lifeless?. in ac mode, the attack and release thresholds are set relative to full-scale. in drc mode, the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is se t relative to the maximum volume setting plus the attack threshold. table 66. limiter attack rate vs lxa bits lxa[3:0] attack rate db/ms 0000 3.1584 fast slow 0001 2.7072 0010 2.2560 0011 1.8048 0100 1.3536 0101 0.9024 0110 0.4512 0111 0.2256 1000 0.1504 1001 0.1123 1010 0.0902 1011 0.0752 1100 0.0645 1101 0.0564 1110 0.0501 1111 0.0451 docid13773 rev 4 51/68 STA333BW register description 68 anticlipping mode table 67. limiter release rate vs lxr bits lxr[3:0] release rate db/ms 0000 0.5116 fast slow 0001 0.1370 0010 0.0744 0011 0.0499 0100 0.0360 0101 0.0299 0110 0.0264 0111 0.0208 1000 0.0198 1001 0.0172 1010 0.0147 1011 0.0137 1100 0.0134 1101 0.0117 1110 0.0110 1111 0.0104 table 68. limiter attack threshold vs lxat bits (ac mode) lxat[3:0] ac (db relative to fs) 0000 -12 0001 -10 0010 -8 0011 -6 0100 -4 0101 -2 0110 0 0111 +2 1000 +3 1001 +4 1010 +5 1011 +6 1100 +7 1101 +8 register description STA333BW 52/68 docid13773 rev 4 dynamic range compression mode 1110 +9 1111 +10 table 69. limiter release threshold vs lxrt bits (ac mode) lxrt[3:0] ac (db relative to fs) 0000 - ? 0001 -29 0010 -20 0011 -16 0100 -14 0101 -12 0110 -10 0111 -8 1000 -7 1001 -6 1010 -5 1011 -4 1100 -3 1101 -2 1110 -1 1111 -0 table 70. limiter attack threshold vs lxat bits (drc mode) lxat[3:0] drc (db relative to volume) 0000 -31 0001 -29 0010 -27 0011 -25 0100 -23 0101 -21 0110 -19 0111 -17 1000 -16 table 68. limiter attack threshold vs lxat bits (ac mode) (continued) lxat[3:0] ac (db relative to fs) docid13773 rev 4 53/68 STA333BW register description 68 1001 -15 1010 -14 1011 -13 1100 -12 1101 -10 1110 -7 1111 -4 table 71. limiter release threshold vs lxrt bits (drc mode) lxrt[3:0] drc (db relati ve to volume + lxat) 0000 - ? 0001 -38 0010 -36 0011 -33 0100 -31 0101 -30 0110 -28 0111 -26 1000 -24 1001 -22 1010 -20 1011 -18 1100 -15 1101 -12 1110 -9 1111 -6 table 70. limiter attack threshold vs lxat bits (drc mode) (continued) lxat[3:0] drc (db relative to volume) register description STA333BW 54/68 docid13773 rev 4 7.7 user-defined coefficient cont rol registers (addr 0x16 - 0x26) 7.7.1 coefficient address register (addr 0x16) 7.7.2 coefficient b1 data register bits (addr 0x17 - 0x19) 7.7.3 coefficient b2 data re gister bits (addr 0x1a - 0x1c) 7.7.4 coefficient a1 data regi ster bits (addr 0x1d - 0x1f) d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved cfa5 cfa4 cfa3 cfa2 cfa1 cfa0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b15 c1b14 c1b13 c1b12 c1b11 c1b10 c1b9 c1b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b7 c1b6 c1b5 c1b4 c1b3 c1b2 c1b1 c1b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b23 c2b22 c2b21 c2b20 c2b19 c2b18 c2b17 c2b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b15 c2b14 c2b13 c2b12 c2b11 c2b10 c2b9 c2b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b7 c2b6 c2b5 c2b4 c2b3 c2b2 c2b1 c2b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c3b23 c3b22 c3b21 c3b20 c3b19 c3b18 c3b17 c3b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c3b15 c3b14 c3b13 c3b12 c3b11 c3b10 c3b9 c3b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c3b7 c3b6 c3b5 c3b4 c3b3 c3b2 c3b1 c3b0 00000000 docid13773 rev 4 55/68 STA333BW register description 68 7.7.5 coefficient a2 data re gister bits (addr 0x20 - 0x22) 7.7.6 coefficient b0 data register bits (addr 0x23 - 0x25) 7.7.7 coefficient read / writ e control register (addr 0x26) d7 d6 d5 d4 d3 d2 d1 d0 c4b23 c4b22 c4b21 c4b20 c4b19 c4b18 c4b17 c4b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b15 c4b14 c4b13 c4b12 c4b11 c4b10 c4b9 c4b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b7 c4b6 c4b5 c4b4 c4b3 c4b2 c4b1 c4b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b23 c5b22 c5b21 c5b20 c5b19 c5b18 c5b17 c5b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b15 c5b14 c5b13 c5b12 c5b11 c5b10 c5b9 c5b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b7 c5b6 c5b5 c5b4 c5b3 c5b2 c5b1 c5b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 reserved ra r1 wa w1 0 0000 register description STA333BW 56/68 docid13773 rev 4 7.7.8 description coefficients for user-defined eq, mixing, scaling, and bass management are handled internally in the STA333BW via ram. access to this ram is available to the user via an i 2 c register interface. a collection of i 2 c registers are dedicated to th is function. one contains a coefficient base address, five sets of three stor e the values of the 24-bit coefficients to be written or that were read, and one contains bi ts used to control the read / write of the coefficient(s) to/from ram. note: the read write operation on ram coefficients works only if rlcki (p in29) is switching and stable (ref. table 8 , tlrjt timing) and pll must be locked (ref bit d7 reg 0x2d). reading a coefficient from ram 1. write 6-bits of address to i 2 c register 0x16. 2. write 1 to r1 bit in i 2 c address 0x26. 3. read top 8-bits of coefficient in i 2 c address 0x17. 4. read middle 8-bits of coefficient in i 2 c address 0x18. 5. read bottom 8-bits of coefficient in i 2 c address 0x19. reading a set of coefficients from ram 1. write 6-bits of address to i 2 c register 0x16. 2. write 1 to ra bit in i 2 c address 0x26. 3. read top 8-bits of coefficient in i 2 c address 0x17. 4. read middle 8-bits of coefficient in i 2 c address 0x18. 5. read bottom 8-bits of coefficient in i 2 c address 0x19. 6. read top 8-bits of coefficient b2 in i 2 c address 0x1a. 7. read middle 8-bits of coefficient b2 in i 2 c address 0x1b. 8. read bottom 8-bits of coefficient b2 in i 2 c address 0x1c. 9. read top 8-bits of coefficient a1 in i 2 c address 0x1d. 10. read middle 8-bits of coefficient a1 in i 2 c address 0x1e. 11. read bottom 8-bits of coefficient a1 in i 2 c address 0x1f. 12. read top 8-bits of coefficient a2 in i 2 c address 0x20. 13. read middle 8-bits of coefficient a2 in i 2 c address 0x21. 14. read bottom 8-bits of coefficient a2 in i 2 c address 0x22. 15. read top 8-bits of coefficient b0 in i 2 c address 0x23. 16. read middle 8-bits of coefficient b0 in i 2 c address 0x24. 17. read bottom 8-bits of coefficient b0 in i 2 c address 0x25. writing a single coefficient to ram 1. write 6-bits of address to i 2 c register 0x16. 2. write top 8-bits of coefficient in i 2 c address 0x17. 3. write middle 8-bits of coefficient in i 2 c address 0x18. 4. write bottom 8-bits of coefficient in i 2 c address 0x19. 5. write 1 to w1 bit in i 2 c address 0x26. docid13773 rev 4 57/68 STA333BW register description 68 writing a set of coefficients to ram 1. write 6-bits of starting address to i 2 c register 0x16. 2. write top 8-bits of coefficient b1 in i 2 c address 0x17. 3. write middle 8-bits of coefficient b1 in i 2 c address 0x18. 4. write bottom 8-bits of coefficient b1 in i 2 c address 0x19. 5. write top 8-bits of coefficient b2 in i 2 c address 0x1a. 6. write middle 8-bits of coefficient b2 in i 2 c address 0x1b. 7. write bottom 8-bits of coefficient b2 in i 2 c address 0x1c. 8. write top 8-bits of coefficient a1 in i 2 c address 0x1d. 9. write middle 8-bits of coefficient a1 in i 2 c address 0x1e. 10. write bottom 8-bits of coefficient a1 in i 2 c address 0x1f. 11. write top 8-bits of coefficient a2 in i 2 c address 0x20. 12. write middle 8-bits of coefficient a2 in i 2 c address 0x21. 13. write bottom 8-bits of coefficient a2 in i 2 c address 0x22. 14. write top 8-bits of coefficient b0 in i 2 c address 0x23. 15. write middle 8-bits of coefficient b0 in i 2 c address 0x24. 16. write bottom 8-bits of coefficient b0 in i 2 c address 0x25. 17. write 1 to wa bit in i 2 c address 0x26. the mechanism for writing a set of coefficient s to ram provides a method of updating the five coefficients corresponding to a given bi quad (filter) simultaneous ly to avoid possible unpleasant acoustic side-effects. when using th is technique, the 6-bit address specifies the address of the biquad b1 coefficient (for ex ample, 0, 5, 10, 20, 35 decimal), and the STA333BW generates the ram addresses as of fsets from this base value to write the complete set of coefficient data. table 72. ram block for biquads, mixing, scaling, bass management index (decimal) index (hex) description coefficient default 0 0x00 channel 1 - biquad 1 c1h10(b1/2) 0x000000 1 0x01 c1h11(b2) 0x000000 2 0x02 c1h12(a1/2) 0x000000 3 0x03 c1h13(a2) 0x000000 4 0x04 c1h14(b0/2) 0x400000 5 0x05 channel 1 - biquad 2 c1h20 0x000000 ?? ? ? ? 19 0x13 channel 1 - biquad 4 c1h44 0x400000 20 0x14 channel 2 - biquad 1 c2h10 0x000000 21 0x15 c2h11 0x000000 ?? ? ? ? 39 0x27 channel 2 - biquad 4 c2h44 0x400000 register description STA333BW 58/68 docid13773 rev 4 user-defined eq the STA333BW can be programmed for four eq filters (biquads) per each of the two input channels. the biquads use the following equation: y[n] = 2 * (b 0 / 2) * x[n] + 2 * (b 1 / 2) * x[n-1] + b 2 * x[n-2] - 2 * (a 1 / 2) * y[n-1] - a 2 * y[n-2] = b 0 * x[n] + b 1 * x[n-1] + b 2 * x[n-2] - a 1 * y[n-1] - a 2 * y[n-2] where y[n] represents the output and x[n] represents the input. multipliers are 24-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7fffff (0.9999998808). 40 0x28 channel 1 / 2 - biquad 5 or 8 for xo = 000 high-pass 2 nd order filter for xo ?? 000 c12h0(b1/2) 0x000000 41 0x29 c12h1(b2) 0x000000 42 0x2a c12h2(a1/2) 0x000000 43 0x2b c12h3(a2) 0x000000 44 0x2c c12h4(b0/2) 0x400000 45 0x2d channel 3 - biquad for xo = 000 low-pass 2 nd order filter for xo ?? 000 c3h0(b1/2) 0x000000 46 0x2e c3h1(b2) 0x000000 47 0x2f c3h2(a1/2) 0x000000 48 0x30 c3h3(a2) 0x000000 49 0x31 c3h4(b0/2) 0x400000 50 0x32 channel 1 - prescale c1pres 0x7fffff 51 0x33 channel 2 - prescale c2pres 0x7fffff 52 0x34 channel 1 - postscale c1psts 0x7fffff 53 0x35 channel 2 - postscale c2psts 0x7fffff 54 0x36 channel 3 - postscale c3psts 0x7fffff 55 0x37 twarn / oc - limit twocl 0x5a9df7 56 0x38 channel 1 - mix 1 c1mx1 0x7fffff 57 0x39 channel 1 - mix 2 c1mx2 0x000000 58 0x3a channel 2 - mix 1 c2mx1 0x000000 59 0x3b channel 2 - mix 2 c2mx2 0x7fffff 60 0x3c channel 3 - mix 1 c3mx1 0x400000 61 0x3d channel 3 - mix 2 c3mx2 0x400000 62 0x3e unused - - 63 0x3f unused - - table 72. ram block for biquads, mixing, scaling, bass management (continued) index (decimal) index (hex) description coefficient default docid13773 rev 4 59/68 STA333BW register description 68 coefficients stored in the user defined coefficient ram are referenced in the following manner: cxhy0 = b 1 / 2 cxhy1 = b 2 cxhy2 = -a 1 / 2 cxhy3 = -a 2 cxhy4 = b 0 / 2 where x represents the channel and the y the biquad number. for example, c2h41 is the b 2 coefficient in the fourth biquad for channel 2. crossover and biquad #8 additionally, the STA333BW can be program med for a high-pass filter (processing channels 1 and 2) and a low-pass filter (processing channel 3) to be used for bass- management crossover when the xo setting is 000 (user-defined). both of these filters when defined by the user (rather than using t he preset crossover filters) are second order filters that use the bi quad equation given above. they are loaded into the c12h0-4 and c3hy0-4 areas of ram noted in table 72 , addresses 0x28 to 0x31. by default, all user-defined filters are pass-throug h where all coefficients are set to 0, except the b 0 / 2 coefficient which is set to 0x400000 (representing 0.5) prescale the STA333BW provides a multiplication for each input channel for the purpose of scaling the input prior to eq. this pre-eq scali ng is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7fffff = 0.9999998808. the scale factor for this multiply is loaded into ram. all channels can use the channel-1 prescale factor by setting the biquad link bit. by default, all presca le factors (ram addresses 0x32 to 0x33) are set to 0x7fffff. postscale the STA333BW provides one additional multiplicat ion after the last interpolation stage and the distortion compensation on each channel. this postscaling is accomplished by using a 24-bit signed fractional multiplier, with 0x 800000 = -1 and 0x7fffff = 0.9999998808. the scale factor for this multiply is loaded into ram. this postscale factor can be used in conjunction with an adc equipped micro-controller to perform power-supply error correction. all channels can use the channel-1 postscale factor by setting the postscale link bit. by default, all postscale factors (ram addresses 0x34 to 0x36) are set to 0x7fffff. when line output is being used, channel-3 postscale affects both channels 3 and 4. thermal warning and overcurrent adjustment (twocl) the STA333BW provides a simple mechanism for reacting to overcurrent or thermal warning detection in the power block. when the warning occurs, the twocl value is used to provide output attenuatio n clipping on all channels. the amount of attenuation to be applied in th is situation can be adjusted by modifying the overcurrent and thermal warning limiting value (ram addr 0x37). by default, the overcurrent postscale adjustment factor is set to 0x5a9df7 (t hat is, -3 db). once the limiting is applied, it remains until the device is reset or accord ing to the twrb and ocrb settings. register description STA333BW 60/68 docid13773 rev 4 7.8 variable max power correcti on registers (addr 0x27 - 0x28) mpcc bits determine the 16 msbs of the mpc co mpensation coefficient. this coefficient is used in place of the default coefficient when mpcv = 1. 7.9 distortion compensation registers (addr 0x29 - 0x2a) dcc bits determine the 16 msbs of the distortion compensation coefficient. this coefficient is used in place of the default coefficient when dccv = 1. 7.10 fault detect recovery consta nt registers (addr 0x2b - 0x2c) fdrc bits specify the 16-bit fault detect recove ry time delay. when fault is asserted, the tristate output is immediately asserted low a nd held low for the time period specified by this constant. a constant value of 0x0001 in this register is approximately 0.083 ms. the default value of 0x000c gives approximately 0.1 ms. note: 0x0000 is a reserved value for these registers. d7 d6 d5 d4 d3 d2 d1 d0 mpcc15 mpcc14 mpcc13 mpcc12 m pcc11 mpcc10 mpcc9 mpcc8 00011010 d7 d6 d5 d4 d3 d2 d1 d0 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 11000000 d7 d6 d5 d4 d3 d2 d1 d0 dcc15 dcc14 dcc13 dcc12 dcc11 dcc10 dcc9 dcc8 11110011 d7 d6 d5 d4 d3 d2 d1 d0 dcc7 dcc6 dcc5 dcc4 dcc3 dcc2 dcc1 dcc0 00110011 d7 d6 d5 d4 d3 d2 d1 d0 fdrc15 fdrc14 fdrc13 fdrc12 fdrc11 fdrc10 fdrc9 fdrc8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 fdrc7 fdrc6 fdrc5 fdrc4 fdrc3 fdrc2 fdrc1 fdrc0 00001100 docid13773 rev 4 61/68 STA333BW register description 68 7.11 device status re gister (addr 0x2d) this read-only register provides fault and ther mal-warning status info rmation from the power control block. logic value 1 for faults or warning means normal state. logic 0 means a fault or warning detected on power bridge. the pllul = 1 means that the pll is not locked. d7 d6 d5 d4 d3 d2 d1 d0 pllul fault uvfault reserved ocfault ocwarn tfault twarn table 73. status register bits bit r/w rst name description 7 r - pllul 0: pll locked 1: pll not locked 6r - fault 0: fault detected on power bridge 1: normal operation 5 r - uvfault 0: vccxx internally detected < undervoltage threshold 4 r - reserved - 3 r - ocfault 0: overcurrent fault detected 2 r - ocwarn 0: overcurrent warning 1 r - tfault 0: thermal fault, junction temperature over limit 0r - twarn 0: thermal warning, junction temperature is close to the fault condition applications STA333BW 62/68 docid13773 rev 4 8 applications 8.1 applications schematic figure 21 below shows the typical applications sch ematic for STA333BW. special attention has to be paid to the layout of the pcb. all the decoupling capacitors have to be placed as close as possible to the device to limit spikes on all the supplies. 8.2 pll filter circuit it is recommended to use the above circuit and va lues for the pll loop filter to achieve the best performance from the device in general app lications. note that the ground of this filter circuit has to be connected to the ground of the pll without any resistive path. concerning the component values, it must be taken into account that the gr eater the filter bandwidth, the less is the lock time but the higher is the pll output jitter. 8.3 typical output configuration figure 20 shows the typical output configuration used for btl stereo mode. please contact stmicroelectronics for other reco mmended output configurations. figure 20. output configuration for stereo btl mode (r l = 8 ?? out1a 100 nf 100 nf 100 nf 100 nf 6r2 6r2 330 pf 22r out1b 22 h 22 h left 470 nf out2a 100 nf 100 nf 100 nf 100 nf 6r2 6r2 330 pf 22r out2b 22 h 22 h right 470 nf STA333BW applications docid13773 rev 4 63/68 figure 21. applications circuit c33 100nf + c14 100f 25v c22 1nf scl sda 3v3 vcc reset c18 100nf r36 0 c30 100nf c21 1f 25v c23 100nf c29 100nf c31 1f 25v intl c32 100nf c13 100nf 3v3 c36 4.7nf r14 2k2 c35 680pf lrcki pwdn 3v3 out2b xti r35 2r2 bicki out2a u4 sta559bw gnd_sub 1 sa 2 test_mode 3 vss 4 vcc_reg 5 out2b 6 gnd2 7 vcc2 8 out2a 9 out1b 10 vcc1 11 gnd1 12 out1a 13 gnd_reg 14 vdd 15 config 16 out3b / ffx3b 17 out3a / ffx3a 18 eapd / out4b 19 twarn / out4a 20 vdd_dig 21 gnd_dig 22 pwrdn 23 vdd_pll 24 filter_pll 25 gnd_pll 26 xti 27 bicki 28 lrcki 29 sdi 30 reset 31 int_line 32 sda 33 scl 34 gnd_dig 35 vdd_dig 36 out1b data out1a r11 10k STA333BW package thermal characteristics STA333BW 64/68 docid13773 rev 4 9 package thermal characteristics using a double-layer pcb the thermal resistance, junction to ambient, with 2 copper ground areas of 3 x 3 cm 2 and with 16 via holes is 24 c/w in natural air convection. the dissipated power within t he device depends primarily on the supply voltage, load impedance and output modulation level. thus, the maximum estimated dissipated power for the STA333BW is: figure 22 shows the power derating curve for the powersso-36 package on pcbs with copper areas of 2 x 2 cm 2 and 3 x 3 cm 2 . figure 22. powersso-3 6 power derating curve 2 x 20 w @ 8 ? , 18 v pd max is approximately 4 w 2 x 9 w + 1 x 20 w @ 4 ? , 8 ? , ? 18 v pd max is approximately 5 w 0 1 2 3 4 5 6 7 8 0 20406080100120140160 0 1 2 3 4 5 6 7 8 0 20406080100120140160 pd (w) tamb ( c) copper area 2x2 cm and via holes sta339bw psso36 copper area 3x3 cm and via holes 0 1 2 3 4 5 6 7 8 0 20406080100120140160 0 1 2 3 4 5 6 7 8 0 0 1 2 3 4 5 6 7 8 0 20406080100120140160 0 1 2 3 4 5 6 7 8 0 20406080100120140160 pd (w) tamb ( c) copper area 2x2 cm and via holes sta339bw psso36 copper area 3x3 cm and via holes STA333BW powersso- docid13773 rev 4 65/68 STA333BW package mechanical data 68 10 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and prod uct status are available at: www.st.com. ecopack ? is an st trademark. figure 23 below shows the package outline and table 74 gives the dimensions. table 74. powersso-36 epd dimensions symbol dimensions in mm dimensions in inches min typ max min typ max a 2.15 - 2.47 0.085 - 0.097 a2 2.15 - 2.40 0.085 - 0.094 a1 0.00 - 0.10 0.00 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 d 10.10 - 10.50 0.398 - 0.413 e 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - f - 2.3 - - 0.091 - g--0.10--0.004 h 10.10 - 10.50 0.398 - 0.413 h--0.40--0.016 k 0 - 8 degrees 0 - 8 degrees l 0.60 - 1.00 0.024 - 0.039 m - 4.30 - - 0.169 - n - - 10 degrees - - 10 degrees o - 1.20 - - 0.047 - q - 0.80 - - 0.031 - s - 2.90 - - 0.114 - t - 3.65 - - 0.144 - u - 1.00 - - 0.039 - x 4.10 - 4.70 0.161 - 0.185 y 6.50 - 7.10 0.256 - 0.280 package mechanical data STA333BW 66/68 docid13773 rev 4 figure 23. powersso-36 epd outline drawing h x 45 docid13773 rev 4 67/68 STA333BW revision history 68 11 revision history table 75. document revision history date revision changes 11-apr-2006 1 initial release. 26-jul-2007 2 added: electrical specifications, digital section power on sequence processing data path application improved: pin description absolute maximum ratings recommended operative conditions output configuration device status register 26-jan-2011 3 updated presentation document status updated to datasheet modified layout of chapter chapter 1: description removed master mute from section 7.2 on page 41 improved presentation of applications circuit in figure 21 on page 63 18-sep-2013 4 added section 4 on page 16 modified note:: the read write operation on ram coefficients works only if rlcki (pin29) is switching and stable (ref. table 8, tlrjt timing) and pll must be locked (ref bit d7 reg 0x2d). on page 56 updated company information appearing on last page of document STA333BW 68/68 docid13773 rev 4 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particul ar purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ? automotive, automotive safe ty or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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